1. Field of the Invention
This invention relates to combinational logic circuits iplemented with logic gates which are a variation of ECL and, more particularly, relates to combinational logic functions such as Exclusive ORs, Adders and Decoders which are implemented with logic gates capable of performing a logical operation involving the complement of an input variable.
Digital computers utilize both combinational and sequential logic circuits in their processing units. Combinational logic circuits perform a predetermined logical operation upon a number of inputs each of whose voltage levels signify at least two different states. The combinational logic circuits promptly produce an immediate output of the result of the logical operation. Typically, combinational logic functions are carried out by intergrated circuit logic gates of the types which are implemented in one of the popular logic families such as transistor-transistor logic, emitter-coupled logic, resistor-transistor logic, emitter-coupled logic, resistor-transistor logic or which are implemented with particularized logic gates such as those disclosed in Z. E. Skokan, "Logic Gate", U.S. Pat. No. 3,643,109. See generally D. A. Hodges et al., Analysis and Design of Digital Integrated Circuits, Chaper 7, "Bipolar Digital Gate Circuits", (McGraw-Hill 1983); and H. W. Gschwind et al., Design of Digital Computers, pp. 64-100. In a typical digital computer, integrated circuit logic gates based on various logic families may be utilized, especially if they are available off the shelf. Where customized circuits are fabricated, due to process limitations or to the desire to simplify the interconnection schemes, it is at times desirable to utilize a single logic family when implementing both combinational and sequential logic circuits. Such a universal logic gate having unique properties and based upon a variation of ECL logic is disclosed in the co-pending application of J. E. Price and L. W. DeClue, "Inverter Function Logic Gate", filed on Mar. 12, 1984 and assigned Ser. No. 588,476. Briefly, an individual inverter function logic gate is capable of performing logical operations on the complement of one or more of the input variables without having to use a discrete inverter or dual level Cascode logic to produce the complement of the input variable. Such individual inverter function logic gates may be combined to fabricate combinational logic circuits which have preferential properties over prior art combinational logic circuits.
Combinational logic circuits include functions such as Exclusive ORs, Decoders, Adders, AND functions and the like. The logical operation of combinational logic circuits are well known, particularly for two-valued Boolean functions. In practice, most integrated circuits are based on such two-valued functions, although tri-state and higher order devices may be implemented. See, e.g., H. W. Gschwind et al., Design of Digital Computers, pp. 42-45 (Springer-Verlag 1975); and D. A. Hodges et al., Analysis and Design of Digital Integrated Circuits, pp. 2-12 (McGraw-Hill 1983). Combinational logic circuits may be implemented generally by means based upon various types of physical effects. Thus, mechanical, electrical, magnetic, optical, acoustic, or cyrogenic means may be used. Electrical implementation, and particularly implementation with integrated circuits fabricated with bipolar logic of inverter function logic format, as described below, is contemplated in the present invention.
When combinational logic circuits are implemented in an integrated circuit format, they are typically based on one or more of the basic bipolar logic families. For high performance digital computers and other applications where high speed is desired, a logic family of choice would be emitter-coupled logic. Combinational circuits implemented in emitter-coupled logic, the bipolar logic family with the highest speed are shown, for example, in the prior art of FIGS. 7-8, 11-12 and 15-16. Commercial examples of ECL-based logic devices are the 8-Bit Comparator Am25LS2521 of Advanced Micro Devices and the One-of-Eight Decoder Am2921 of Advanced Micro Devices .
For conventional ECL-based combinational circuits, it is the prevailing practice to accomplish the AND function in positive notation by connecting together certain collectors of transistors within the ECL gate; this practice is called collector dotting. See A. H. Seidman, Integrated Circuits Handbook, pp. 74-75 (Wiley 1983). Whenever collector dotting is utilized it is usually necessary to employ a diode clamp (diode 81 in FIG. 8; diodes 144 and 146 in FIG. 16) to prevent excessive currents from passing through load resistors. Also, whenever the complement of an input function is to be included in the logical operation of the circuit, it is necessary to utilize either a separate inverter or a dual level Cascode logic arrangement. And, the number of gates required to implement combinational logic functions in conventional ECL-based logic may be undesirably high.
It is therefore an object of the present invention to provide a combinational logic circuit which incorporates a variation of an ECL logic gate which does not require the use of a diode clamp when collector dotting is utilized in the circuit.
It is another object of the present invention to provide a combinational logic circuit which will allow a logical operation to be carried out on the input signals including the complement of an input signal without the use of a separate inverter or a Cascode logic arrangement.
It is yet another object of the present invention to provide a combinational logic circuit which implements combinational logic functions with fewer gates than conventional ECL-based logic gates.
It is still another object of the present invention to provide a combinational logic circuit which does not require the distribution of a V.sub.BB supply line to the gate.